Low-Dimensional Electronics Translation Program

The National Science Foundation is seeking an Ecosystem Coordinator and Expert Performer Teams for a six-year, $150 million Other Transaction Agreement program advancing low-dimensional semiconductor materials, manufacturing processes, full-chip demonstrations, manufacturing readiness, and AI-enabled acceleration.

United States of America > NATIONAL SCIENCE FOUNDATION > DIRECTORATE FOR TECHNOLOGY, INNOVATION, & PARTNERSHIPS


General
Open (active)
NSF-OTASO-FY26-ELEGANT
Dec 18, 2026 10:00 PM
Sep 17, 2026 06:16 PM
$150,000,000.00
2 years base + 2 × 2 years options
Request for Proposal (RFP)
Federal
Ask AI about this solicitation
Contact
pkbreen@nsf.gov
401 Dulany Street, Alexandria, VA, USA
Submission Instructions
Email
Description

The National Science Foundation is soliciting proposals for the ELEGANT program, which will translate low-dimensional semiconductor technologies from laboratory demonstrations into industrially viable platforms. NSF is seeking proposals from U.S.-based incorporated entities for either an Ecosystem Coordinator role or Expert Performer Teams addressing one or more of five themes: manufacturable materials platforms; process technology and process design kits; device, circuit, and full-chip demonstrations; manufacturing readiness and transition; and AI-enabled acceleration. The program anticipates up to $150 million in NSF funding over three successive 24-month phases. Planned work includes wafer-scale material synthesis and metrology at 200 mm and 300 mm, semiconductor process development and PDK release, functional full-chip prototypes demonstrating at least a 10X PPAC improvement, manufacturing cost and yield modeling, domestic supply-chain and packaging readiness, and a shared AI/ML platform. Proposals must include the required technical, management, budget, personnel, IP/data, and commitment materials and must be submitted as a single PDF.

Classification Codes
NAICS541713Research and Development in Nanotechnology
PSCAJ12PHYSICAL SCIENCES - APPLIED RESEARCH/EXPLORATORY DEVELOPMENT
Smart Codes
semiconductor research and developmentmicroelectronics process developmentai-enabled chip design
Specifications
Service Only
Timeline
Sep 17, 2026 06:16 PM-Published Date
Oct 15, 2026 09:00 PM-Questions Due Date
Dec 18, 2026 10:00 PM-Proposal Due Date
Jan 2, 2027-Inactive Date
Requirements
Scored
No
Documents
TitleDate Posted
ELEGANT OTASO 9 17 2026 Final.pdfSep 17, 2026 12:00 PM
Elegant Additional Materials 9 17 2026 Final.pdfSep 17, 2026 12:00 PM
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